Talk:cpp/thread/hardware destructive interference size

Clarification
I think more wording could help, but I want to be sure I'm correct. Is the idea that one would want to have multiple objects aligned to  and size not more than that in order to ensure they are on the same cache line? The idea being that you can write higher-performance code when you know you'll want to access  and   (in the example) in quick succession?

Likewise for, having that alignment and not more than that size means that two structs will be on separate cache lines and so two threads can hammer on two instances all they want without the cache line bouncing between cores?

I feel like some examples showing expected multi-threaded use would help clarify where one would use each of these. BenFrantzDale (talk) 08:35, 27 March 2021 (PDT)


 * The real effect of std could be demonstrated by the following (pleonastic) code. WIP.